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2.5 v to 5.5 v, 400 a, quad voltage output, 8-/10-/12-bit dacs in 16-lead tssop ad5307/ad5317/ad5327 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features ad5307: 4 buffered 8-bit dacs in 16-lead tssop a version: 1 lsb inl; b version: 0.625 lsb inl ad5317: 4 buffered 10-bit dacs in 16-lead tssop a version: 4 lsb inl; b version: 2.5 lsb inl ad5327: 4 buffered 12-bit dacs in 16-lead tssop a version: 16 lsb inl; b version: 10 lsb inl low power operation: 400 a @ 3 v, 500 a @ 5 v 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power down to 90 na @ 3 v, 300 na @ 5 v ( ldac pin) double-buffered input logic buffered/unbuffered reference input options output range: 0 v to v ref or 0 v to 2 v ref power-on reset to 0 v simultaneous update of outputs ( ldac pin) asynchronous clear facility ( clr pin) low power, spi?-, qspi?-, microwire?-, and dsp- compatible 3-wire serial interface sdo daisy-chaining option on-chip rail-to-rail output buffer amplifiers temperature range of ?40c to +105c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control general description the ad5307/ad5317/ad5327 1 are quad 8-,10-,12-bit buffered voltage-output dacs in 16-lead tssop that operate from single 2.5 v to 5.5 v supplies and consume 400 a at 3 v. their on- chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 v/s. the ad5307/ad5317/ad5327 utilize versatile 3-wire serial interfaces that operate at clock rates up to 30 mhz; these parts are compatible with standard spi, qspi, microwire, and dsp interface standards. the references for the four dacs are derived from two reference pins (one per dac pair). these reference inputs can be configured as buffered or unbuffered inputs. each part incorporates a power- on reset circuit, ensuring that the dac outputs power up to 0 v and remain there until a valid write to the device takes place. there is also an asynchronous active low clr pin that clears all dacs to 0 v. the outputs of all dacs can be updated simul- taneously using the asynchronous ldac input. each part contains a power-down feature that reduces the current consumption of the device to 300 na @ 5 v (90 na @ 3 v). the parts can also be used in daisy-chaining applications using the sdo pin. all three parts are offered in the same pinout, allowing users to select the amount of resolution appropriate for their application without redesigning their circuit board. functional block diagram v dd v ref ab v ref cd power-on reset power-down logic gnd ad5307/ad5317/ad5327 ldac pd ldac clr dcen sdo din sync sclk buffer buffer buffer buffer input register dac register string dac d input register dac register string dac c input register dac register string dac b input register dac register string dac a v out d v out c v out b v out a gain-select logic interface logic 02067-001 figure 1. 1 protected by u.s. patent no. 5,969,657; other pa tents pending.
ad5307/ad5317/ad5327 rev. c | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 ter mi nolo g y .................................................................................... 13 transfer function ........................................................................... 14 functional description .................................................................. 15 digital-to-analog section ......................................................... 15 resistor string ............................................................................. 15 dac reference inputs ............................................................... 15 output amplifier ........................................................................ 16 power-on reset .......................................................................... 16 serial interface ................................................................................ 17 input shift register .................................................................... 17 control bits ................................................................................. 17 low power serial interface ....................................................... 18 daisy chaining ........................................................................... 18 double-buffered interface ........................................................ 18 load dac input ( ldac ) .......................................................... 18 power-down mode .................................................................... 18 microprocessor interfacing ....................................................... 19 applications ..................................................................................... 20 typical application circuit ....................................................... 20 driving v dd from the reference voltage ................................ 20 bipolar operation ....................................................................... 20 opto-isolated interface for process-control applications ... 21 decoding multiple ad5307/ad5317/ad5327 devices ....... 21 ad5307/ad5317/ad5327 as digitally programmable window detectors ..................................................................... 21 daisy chaining ........................................................................... 22 power supply bypassing and grounding ................................ 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 25 revision history 3/06rev. b to rev. c changes to table 3............................................................................ 5 changes to ordering guide .......................................................... 25 10/05rev. a to rev. b updated format..................................................................universal changes to bipolar operation section ........................................ 21 changes to ordering guide .......................................................... 25 8/03rev. 0 to rev. a added a version ................................................................universal changes to features ..........................................................................1 changes to specifications.................................................................2 changes to absolute maximum ratings........................................6 changes to ordering guide .............................................................6 changes to tpc 21......................................................................... 12 added octals section to table ii .................................................. 20 updated outline dimensions....................................................... 21
ad5307/ad5317/ad5327 rev. c | page 3 of 28 specifications v dd = 2.5 v to 5.5 v, v ref = 2 v, r l = 2 k to gnd, c l = 200 pf to gnd. all specifications t min to t max , unless otherwise noted. table 1. a version 1 b version parameter 2 min typ max min typ max unit conditions/comments dc performance 3 , 4 ad5307 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5317 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5327 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 5 60 5 60 mv v dd = 4.5 v, gain = 2; see figure 29 and figure 30 gain error 0.3 1.25 0.3 1.25 % fsr v dd = 4.5 v, gain = 2; see figure 29 and figure 30 lower dead band 5 10 60 10 60 mv see figure 29 , lower dead band exists only if offset error is negative upper dead band 10 60 10 60 mv see figure 30 , upper dead band exists only if v ref = v dd and offset plus gain error is positive offset error drift 6 ?12 ?12 ppm of fsr/c gain error drift ?5 ?5 ppm of fsr/c dc power supply rejection ratio ?60 ?60 db ?v dd = 10% dc crosstalk 200 200 mv r l = 2 k to gnd or v dd dac reference inputs v ref input range 1 v dd 1 v dd v buffered reference mode 0.25 v dd 0.25 v dd v unbuffered reference mode v ref input impedance (r dac ) >10 >10 m bu ffered reference mode and power-down mode 74 90 74 90 k unbuffered reference mode, 0 v to v ref output range 37 45 37 45 k unbuffered reference mode, 0 v to 2 v ref output range reference feedthrough ?90 ?90 db frequency = 10 khz channel-to-channel isolation ?75 ?75 db frequency = 10 khz output characteristics minimum output voltage 7 0.001 0.001 v a measure of the minimum drive capability of the output amplifier maximum output voltage v dd ? 0.001 v dd ? 0.001 v a measure of the maximum drive capability of the output amplifier dc output impedance 0.5 0.5 short-circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 s coming out of power-down mode, v dd = 5 v 5 5 s coming out of power-down mode, v dd = 3 v
ad5307/ad5317/ad5327 rev. c | page 4 of 28 a version 1 b version parameter 2 min typ max min typ max unit conditions/comments logic inputs input current 1 1 ma input low voltage, v il 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v input high voltage, v ih (excluding dcen) 1.7 1.7 v v dd = 2.5 v to 5.5 v; ttl and 1.8 v cmos compatible input high voltage, v ih (dcen) 2.4 2.4 v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf logic output (sdo) v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd ? 1 v dd ? 1 v i source = 2 ma v dd = 2.5 v to 3.6 v output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd ? 0.5 v dd ? 0.5 v i source = 2 ma floating state leakage current 1 1 a dcen = gnd floating state output capacitance 3 3 pf dcen = gnd power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 8 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 500 900 500 900 a v dd = 2.5 v to 3.6 v 400 750 400 750 a all dacs in unbuffered mode; in buffered mode, extra current is typically x ma per dac, where x = 5 ma + v ref /r dac i dd (power-down mode) v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.3 1 0.3 1 a v dd = 2.5 v to 3.6 v 0.09 1 0.09 1 a 1 temperature range (a, b versions): ?40c to +105c; ty pical at +25c. 2 see the terminology section. 3 dc specifications tested with the outputs unloaded, unless otherwise noted. 4 linearity is tested using a reduced code range: ad5307 (code 8 to code 255); ad5317 (code 28 to code 1023); ad5327 (code 115 t o code 4095). 5 this corresponds to x codes, where x = deadband voltage/lsb size. 6 guaranteed by design and characterization; not production tested. 7 for the amplifier output to reach its minimum voltage, offset error must be negative. for the amplifier output to reach its ma ximum voltage, v ref = v dd and offset plus gain error must be positive. 8 interface inactive. all dacs active. dac outputs unloaded.
ad5307/ad5317/ad5327 rev. c | page 5 of 28 ac characteristics v dd = 2.5 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd. all specifications t min to t max , unless otherwise noted. table 2. a, b versions 1 parameter 2 , 3 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5307 6 8 s 1/4 scale to 3/ 4 scale change (0x40 to 0xc0) ad5317 7 9 s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5327 8 10 s 1/4 scale to 3/ 4 scale change (0x400 to 0xc00) slew rate 0.7 v/s major-code change glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s sdo feedthrough 4 nv-s daisy-chain mode; sdo load is 10 pf digital crosstalk 0.5 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p; unbuffered mode total harmonic distortion ?70 db v ref = 2.5 v 0.1 v p-p; frequency = 10 khz 1 temperature range (a, b versions): ?40c to +105c; ty pical at +25c. 2 guaranteed by design and characterization; not production tested. 3 see the terminology section. timing characteristics v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. a, b versions parameter 1 , , 2 3 limit at t min , t max unit conditions/comments t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync to sclk falling edge set-up time t 5 5 ns min data set-up time t 6 4.5 ns min data hold time t 7 5 ns min sclk falling edge to sync rising edge t 8 50 ns min minimum sync high time t 9 20 ns min ldac pulse width t 10 20 ns min sclk falling edge to ldac rising edge t 11 20 ns min clr pulse width t 12 0 ns min sclk falling edge to ldac falling edge t 13 4 , 5 20 ns max sclk rising edge to sdo valid (v dd = 3.6 v to 5.5 v) 25 ns max sclk rising edge to sdo valid (v dd = 2.5 v to 3.5 v) t 14 5 ns min sclk falling edge to sync rising edge t 15 8 ns min sync rising edge to sclk rising edge t 16 0 ns min sync rising edge to ldac falling edge 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 3 and figure 4. 4 this is measured with the load circuit of figure 2. t 13 determines maximum sclk freq uency in daisy-chain mode. 5 daisy-chain mode only.
ad5307/ad5317/ad5327 rev. c | page 6 of 28 2ma i ol 2ma i oh v oh (min) to output pin c l 50pf 02067-002 figure 2. load circuit for digital output (sdo) timing specifications 02067-003 sclk din db15 db0 t 4 t 1 t 3 t 2 t 8 t 7 t 9 t 12 t 10 t 11 t 6 t 5 ldac 1 ldac 2 clr sync notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. figure 3. serial interface timing diagram sclk din db15 db0 db15' db0' db0 sdo input word for dac n input word for dac (n+1) undefined input word for dac n db15 t 1 sync ldac t 2 t 3 t 4 t 5 t 6 t 8 t 9 t 13 t 14 t 15 t 16 02067-004 figure 4. daisy-chai ning timing diagram
ad5307/ad5317/ad5327 rev. c | page 7 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter 1 ratings v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v v out a ? v out d to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (a, b versions) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c 16-lead tssop power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w reflow soldering peak temperature 220c time at peak temperature 10 sec to 40 sec 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad5307/ad5317/ad5327 rev. c | page 8 of 28 pin configuration and fu nction descriptions top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v dd v out a v out b v out c v ref ab v ref cd sdo sclk din gnd v out d dcen ad5307/ ad5317/ ad5327 clr ldac pd sync 02067-005 figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 clr active low control input. loads all 0s to all input and dac registers. therefore, the outputs also go to 0 v. 2 ldac active low control input. transfers the contents of the in put registers to their respective dac registers. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied permanently low. 3 v dd power supply input. these parts can be operated from 2.5 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 v out a buffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 5 v out b buffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 6 v out c buffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 7 v ref ab reference input pin for dac a and dac b. it can be configured as a buffered or unbuffered input to each or both of the dacs, depending on the state of the buf bits in the seri al input words to dac a and dac b. it has an input range of 0.25 v to v dd in unbuffered mode and 1 v to v dd in buffered mode. 8 v ref cd reference input pin for dac c and dac d. it can be configured as a buffered or unbuffered input to each or both of the dacs, depending on the state of the buf bits in the seri al input words to dac c and dac d. it has an input range of 0.25 v to v dd in unbuffered mode and 1 v to v dd in buffered mode. 9 dcen enables the daisy-chaining option. it should be tied high if th e part is being used in a daisy chain, and tied low if it is being used in standalone mode. 10 pd active low control input. it acts like a hardware power-down option. all dacs go into power-down mode when this pin is tied low. the dac outputs go into a high impedanc e state, and the current consumption of the part drops to 300 na @ 5 v (90 na @ 3 v). 11 v out d buffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 din serial data input. these devices each have a 16-bit shift regist er. data is clocked into the re gister on the falling edge of the serial clock input. the din input buffer is powered down after each write cycle. 14 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 30 mhz. the sclk inp ut buffer is powered down after each write cycle. 15 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift regi ster. data is transferred in on the falling edges of the following 16 clocks. if sync is taken high before the 16th falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 16 sdo serial data output. can be used for dais y-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. the serial data is transferred on the rising edge of sclk and is valid on the falling edge of the clock.
ad5307/ad5317/ad5327 rev. c | page 9 of 28 typical performance characteristics 02067-006 0 50 100 150 200 ?1.0 ?0.5 0 0.5 1.0 250 code inl error (lsb) t a = 25c v dd = 5v figure 6. ad5307 inl 02067-007 0 200 400 600 900 ?3 ?2 ?1 0 1 2 3 1000 code inl error (lsb) t a = 25c v dd = 5v figure 7. ad5317 inl 02067-008 0 1000 2000 3000 ?12 ?8 ?4 0 4 8 12 4000 code inl error (lsb) t a = 25c v dd = 5v figure 8. ad5327 inl 02067-009 0 50 100 150 200 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 250 code dnl error (lsb) t a = 25c v dd = 5v figure 9. ad5307 dnl 02067-010 0 200 400 600 800 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1000 code dnl error (lsb) t a = 25c v dd = 5v figure 10. ad5317 dnl 02067-011 0 1000 2000 3000 ?1.0 ?0.5 0 0.5 1.0 4000 code dnl error (lsb) t a = 25c v dd = 5v figure 11. ad5327 dnl
ad5307/ad5317/ad5327 rev. c | page 10 of 28 02067-012 0123 ?0.50 ?0.25 0 0.25 0.50 45 v ref (v) error (lsb) max inl min inl min inl t a = 25c v dd = 5v max dnl figure 12. ad5307 inl error and dnl error vs. v ref 02067-013 ?40 0 40 80 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.4 0.3 0.2 0.1 0.5 120 temperature (c) error (lsb) max inl max dnl v dd = 5v v ref = 3v min inl min dnl figure 13. ad5307 inl error and dnl error vs. temperature 02067-014 ?40 0 40 80 ?1.0 ?0.5 0 0.5 1.0 120 temperature (c) error (% fsr) v dd = 5v v ref = 2v gain error offset error figure 14. ad5307 offset error and gain error vs. temperature 02067-015 012345 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.1 0 6 v dd (v) error (% fsr) gain error offset error 0.2 t a = 25c v ref = 2v figure 15. offset error and gain error vs. v dd 02067-016 012345 0 1 2 3 4 5 6 sink/source current (ma) v out (v) 5v source 3v source 5v sink 3v sink figure 16. v out source and sink current capability 02067-017 zero scale 0 100 200 300 400 500 full scale code i dd (a) t a = 25c v dd = 5v v ref = 2v 600 figure 17. supply current vs. dac code
ad5307/ad5317/ad5327 rev. c | page 11 of 28 02067-018 0 100 200 300 400 500 v dd (v) i dd (a) 600 2.5 3.0 3.5 4.0 4.5 5.0 5.5 +25c ?40c +105c figure 18. supply current vs. supply voltage 02067-019 0 0.1 0.2 0.3 0.4 0.5 v dd (v) i dd (a) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 +105c +25c ?40c figure 19. power-down current vs. supply voltage 02067-020 300 400 500 600 700 800 v logic (v) i dd (a) 01 2 34 5 increasing t a = 25c decreasing v dd = 5v increasing decreasing v dd = 3v figure 20. supply current vs. logic input voltage for sclk and din increasing and decreasing 02067-021 ch2 ch1 ch1 1v, ch2 5v, time base = 1s/div t a = 25c v dd = 5v v ref = 5v v out a sclk figure 21. half-scale settling (1/4 to 3/4 scale code change) ch1 2.00v, ch2 200mv, time base = 200s/div 02067-022 t a = 25c v dd = 5v v ref = 2v v out a v dd ch1 ch2 figure 22. power-on reset to 0 v 02067-023 t a = 25c v dd = 5v v ref = 2v ch1 500mv, ch2 5.00v, time base = 1s/div ch1 ch2 v out a pd figure 23. exiting po wer-down to midscale
ad5307/ad5317/ad5327 rev. c | page 12 of 28 02067-024 350 400 450 500 550 600 i dd (a) frequency v dd = 5v v dd = 3v figure 24. i dd histogram with v dd = 3 v and v dd = 5 v 02067-025 2.47 2.48 2.49 2.50 1s/div v out (v) figure 25. ad5327 major-code transition glitch energy 02067-026 10 100 1k 10k 100k 1m ?60 ?50 ?40 ?30 ?20 ?10 0 10 10m frequency (hz) (db) figure 26. multiplying bandwidth (small-signal frequency response) 02067-027 012345 ?0.02 0.02 6 ?0.01 0 0.01 v ref (v) full-scale error (v) v dd = 5v t a = 25c figure 27. full-scale error vs. v ref 02067-028 150ns/div 1mv/div figure 28. dac-to -dac crosstalk
ad5307/ad5317/ad5327 rev. c | page 13 of 28 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation in lsb from a straight line passing through the endpoints of the dac transfer function. figure 6 through figure 8 show plots of typical inl vs. code. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. figure 9 through figure 11 show plots of typical dnl vs. code. offset error offset error is a measure of the deviation in the output voltage from 0 v when zero-code is loaded to the dac (see figure 29 and figure 30 .) it can be negative or positive. it is expressed in millivolts. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift offset error drift is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full- scale range)/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full- scale range)/c. dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. it is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v, and v dd is varied 10%. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in microvolts. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels. channel-to-channel isolation channel-to-channel isolation is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in decibels. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, but it is measured when the dac is not being written to ( sync held high). it is specified in nv-s and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping ldac high, and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s or vice versa) with ldac low while monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth, and the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
ad5307/ad5317/ad5327 rev. c | page 14 of 28 transfer function dac code gain error + offset erro r output voltage negative offset error negative offset error amplifier footroom l o w e r d e a d b a n d c o d e s 02067-029 a c t u a l i d e a l figure 29. transfer functi on with negative offset 02067-030 actual ideal dac code full scale positive offset error output v oltage gain error + offset error upper deadband codes figure 30. transfer function with positive offset (v ref = v dd )
ad5307/ad5317/ad5327 rev. c | page 15 of 28 functional description the ad5307/ad5317/ad5327 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits respectively. each contains four output buffer amplifiers and is written to via a 3-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/s. dac a and dac b share a common reference input, v ref ab. dac c and dac d share a common reference input, v ref cd. each reference input can be buffered to draw virtually no current from the reference source, or can be unbuffered to give a reference input range of 0.25 v to v dd . the devices have a power-down mode in which all dacs can be completely turned off with a high impedance output. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the corresponding dac. figure 31 shows a block diagram of the dac architecture. because the input coding to the dac is straight binary, the ideal output voltage is given by n ref out dv v 2 = where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 255 for ad5307 (8 bits). 0 to 1023 for ad5317 (10 bits). 0 to 4095 for ad5327 (12 bits). n is the dac resolution. input register dac register resistor string output buffer amplifier reference buffer buf gain mode (gain = 1 or 2) v ref ab v out a 02067-031 figure 31. single dac channel architecture resistor string the resistor string section is shown in figure 32 . it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. dac reference inputs there is a reference pin for each pair of dacs. the reference inputs are buffered but can also be individually configured as unbuffered. the advantage with the buffered input is the high impedance it presents to the voltage source driving it. however, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 v and as high as v dd , because there is no restriction due to headroom and footroom of the reference amplifier. r r r r r to output amplifier 02067-032 figure 32. resistor string if there is a buffered reference in the circuit (for example, ref192), there is no need to use the on-chip buffers of the ad5307/ad5317/ ad5327. in unbuffered mode, the input impedance is still large at typically 90 k per reference input for 0 v to v ref mode and 45 k or 0 v to 2 v ref mode. the buffered/unbuffered option is controlled by the buf bit in the data-word. the buf bit setting applies to whichever dac is selected.
ad5307/ad5317/ad5327 rev. c | page 16 of 28 output amplifier the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail. its actual range depends on the value of v ref , gain, offset error, and gain error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . because of clamping, however, the maximum output is limited to v dd ? 0.001 v. the output amplifier is capable of driving a load of 2 k to gnd or v dd in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in figure 16 . the slew rate is 0.7 v/s, with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s. power-on reset the ad5307/ad5317/ad5327 are each provided with a power- on reset function so that they power up in a defined state. the power-on state is ? normal operation ? reference inputs unbuffered ? 0 v to v ref output range ? output voltage set to 0 v both input and dac registers are filled with 0s until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up.
ad5307/ad5317/ad5327 rev. c | page 17 of 28 serial interface the ad5307/ad5317/ad5327 are controlled over versatile 3-wire serial interfaces that operate at clock rates of up to 30 mhz and are compatible with spi, qspi, microwire, and dsp interface standards. input shift register the input shift register is 16 bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this operation is shown in figure 3 . the 16-bit word consists of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. data is loaded msb first (bit 15), and the first two bits determine whether the data is for dac a, dac b, dac c, or dac d. bit 13 and bit 12 control the operating mode of the dac. bit 13 is gain, which determines the output range of the part. bit 12 is buf, which controls whether the reference inputs are buffered or unbuffered. table 6. address bits for the ad53x7 a1 (bit 15) a0 (bit 14) dac addressed 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d control bits gain controls the output range of the addressed dac. 0: output range of 0 v to v ref . 1: output range of 0 v to 2 v ref . buf controls whether reference of the addressed dac is buffered or unbuffered. 0: unbuffered reference. 1: buffered reference. the ad5327 uses all 12 bits of dac data; the ad5317 uses 10 bits and ignores the 2 lsbs. the ad5307 uses eight bits and ignores the last four bits. the data format is straight binary, with all 0s corresponding to 0 v output and all 1s corresponding to full-scale output (v ref ? 1 lsb). the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can be transferred into the device only while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync to sclk falling edge set-up time, t 4 . after sync goes low, serial data is shifted into the devices input shift register on the falling edges of sclk for 16 clock pulses. in standalone mode (dcen = 0), any data and clock pulses after the 16th falling edge of sclk are ignored, and no further serial data transfer can occur until sync is taken high and low again. sync can be taken high after the falling edge of the 16th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of serial data transfer, data is automatically trans- ferred from the input shift register to the input register of the selected dac. if sync is taken high before the 16th falling edge of sclk, the data transfer is aborted and the dac input registers are not updated. when data has been transferred into the input register of a dac, the corresponding dac register and dac output can be updated by taking ldac low. clr is an active low, asynchronous clear that clears the input registers and dac registers to all 0s. bit 15 (msb) bit 0 (lsb) a1 buf d7 d6 d5 d4 d3 d2 d1 d0 gain a0 xxxx data bits 02067-033 figure 33. ad5307 input shift register contents bit 15 (msb) bit 0 (lsb) a1 buf d9 d8 d7 d6 d5 d4 d3 d2 gaina0 d1 d0 x x data bits 02067-034 figure 34. ad5317 input shift register contents bit 15 (msb) bit 0 (lsb) a1 buf d11 d10 d9 d8 d7 d6 d5 d4 gaina0 d3 d2 d1 d0 data bits 02067-035 figure 35. ad5327 input shift register contents
ad5307/ad5317/ad5327 rev. c | page 18 of 28 low power serial interface to minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . the sclk and din input buffers are powered down on the rising edge of sync . daisy chaining for systems that contain several dacs, or where the user wishes to read back the dac contents for diagnostic purposes, the sdo pin can be used to daisy-chain several devices together and provide serial readback. by connecting the dcen (daisy-chain enable) pin high, the daisy-chain mode is enabled. it is tied low in the case of standalone mode. in daisy-chain mode, the internal gating on sclk is disabled. the sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the din input on the next dac in the chain, a multi-dac interface is constructed. each dac in the system requires 16 clock pulses; therefore, the total number of clock cycles must equal 16n, where n is the total number of devices in the chain. when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data from being clocked into the input shift register. a continuous sclk source can be used if sync is held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles can be used and sync can be taken high some time later. when the transfer to all input registers is complete, a common ldac signal updates all dac registers and all analog outputs are updated simultaneously. double-buffered interface the ad5307/ad5317/ad5327 dacs have double-buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. access to the dac registers is controlled by the ldac pin. when the ldac pin is high, the dac registers are latched and the input registers can change state without affecting the contents of the dac registers. when ldac is brought low, however, the dac registers become transparent and the contents of the input registers are transferred to them. the double-buffered interface is useful if the user requires simultaneous updating of all dac outputs. the user can write to three of the input registers individually and then, by bringing ldac low when writing to the remaining dac input register, all outputs update simultaneously. these parts each contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5307/ad5317/ad5327, the dac register updates only if the input register has changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. load dac input (ldac ) ldac transfers data from the input registers to the dac registers and therefore updates the outputs. use of the ldac function enables double buffering of the dac data, gain, and buf. there are two ldac modes: synchronous and asynchronous. synchronous mode in this mode, the dac registers are updated after new data is read from on the falling edge of the 16th sclk pulse. ldac can be tied permanently low or pulsed as in figure 3 . asynchronous mode in this mode, the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. power-down mode the ad5307/ad5317/ad5327 have low power consumption, typically dissipating 1.2 mw with a 3 v supply and 2.5 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power-down mode, which is selected by taking the pd pin low. when the pd pin is high, all dacs work normally with a typical power consumption of 500 a at 5 v (400 a at 3 v). however, in power-down mode, the supply current falls to 300 na at 5 v (90 na at 3 v) when all dacs are powered down. not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it an open circuit. this has the advantage that the output is three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illustrated in figure 36 . the bias generator, output amplifiers, resistor string, and all other associated linear circuitry are shut down when the power- down mode is activated. however, the contents of the registers are unaffected when in power-down. in fact, it is possible to load new data to the input registers and dac registers during power-down. the dac outputs update as soon as pd goes high.
ad5307/ad5317/ad5327 rev. c | page 19 of 28 the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from the rising edge of pd to when the output voltage deviates from its power-down voltage. see figure 23 for a plot. resistor string dac power-down circuitry amplifier v out 02067-036 figure 36. output stage during power-down microprocessor interfacing adsp-2101/adsp-2103-to- ad5307/ad5317/ad5327 interface figure 37 shows a serial interface between the ad5307/ad5317/ ad5327 and the adsp-2101/adsp-2103. the adsp-2101/ adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal cl ock operation, active low framing, 16-bit word length. transmission is initiated by writing a word to the tx register after sport is enabled. the data is clocked out on each rising edge of the dsps serial clock and clocked into the ad5307/ad5317/ad5327 on the falling edge of the dacs sclk. sclk din sync tfs dt sclk adsp-2101/ adsp-2103 1 1 additional pins omitted for clarity. 02067-037 ad5307/ ad5317/ ad5327 1 figure 37. adsp-2101/adsp-2103-to- ad5307/ad5317/ad5327 interface 68hc11/68l11-to-ad5307/ ad5317/ad5327 interface figure 38 shows a serial interface between the ad5307/ad5317/ ad5327 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5307/ad5317/ ad5327, and the mosi output drives the serial data line (din) of the dac. the sync signal is derived from a port line (pc7). the set-up conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be configured so that its cpol bit is 0 and its cpha bit is 1. when data is being transmitted to the dac, the sync line is taken low (pc7). with this configuration, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes, with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5307/ad5317/ad5327, pc7 is left low after the first eight bits are transferred and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. din sclk sync pc7 sck mosi 68hc11/68l11 1 1 additional pins omitted for clarity. 0 2 0 6 7 - 0 3 8 ad5307/ ad5317/ ad5327 1 figure 38. 68hc11/68l11-to-ad5307/ad5317/ad5327 interface 80c51/80l51-to-ad5307/ad5317/ad5327 interface figure 39 shows a serial interface between the ad5307/ad5317/ ad5327 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5307/ad5317/ad5327, and rxd drives the serial data line of the part. the sync signal is again derived from a bit- programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5307/ad5317/ ad5327, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data lsb first. the ad5307/ad5317/ad5327 require their data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. din sclk p3.3 txd rxd 80c51/80l51 1 02067-039 sync ad5307/ ad5317/ ad5327 1 1 additional pins omitted for clarity. figure 39. 80c51/80l51-to-ad5307/ad5317/ad5327 interface microwire-to-ad5307/ad 5317/ad5327 interface figure 40 shows an interface between the ad5307/ad5317/ ad5327 and a microwire-compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the ad5307/ad5317/ad5327 on the rising edge of sk, which corresponds to the falling edge of the dacs sclk. din sclk sk so microwire 1 1 additional pins omitted for clarity. 02067-040 cs sync ad5307/ ad5317/ ad5327 1 figure 40. microwire-to-ad5307/ad5317/ad5327 interface
ad5307/ad5317/ad5327 rev. c | page 20 of 28 applications typical application circuit the ad5307/ad5317/ad5327 can be used with a wide range of reference voltages and offer full, one-quadrant multiplying capability over a reference range of 0.25 v to v dd . more typically, these devices are used with a fixed precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external refer- ence would be the ad589, a 1.23 v band gap reference. figure 41 shows a typical setup for the ad5307/ad5317/ad5327 when using an external reference. 1f 10f sclk din gnd ad5307/ad5317/ ad5327 serial interface ext ref 02067-041 v dd = 2.5v to 5.5 v ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v in v out sync v out a v out b v out c v out d v ref ab v ref cd 0.1f figure 41. ad5307/ad5317/ad5327 using a 2.5 v external reference driving v dd from the reference voltage if an output range of 0 v to v dd is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to v dd . because this supply can be noisy and not very accurate, the ad5307/ad5317/ad5327 can be powered from the reference voltage, for example, from a 5 v reference such as the ref195, which outputs a steady supply voltage. the typical current required from the ref195 with no load on the dac outputs is 500 a supply current and 112 a into the reference inputs (if unbuffered). when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required with a 10 k load on each output is 612 a + 4 (5 v/10 k) = 2.6 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.2 ppm (26 v) for the 2.6 ma current drawn from it. this corresponds to a 0.0013 lsb error at eight bits and a 0.021 lsb error at 12 bits. bipolar operation the ad5307/ad5317/ad5327 are designed for single-supply operation, but a bipolar output range is also possible using the circuit shown in figure 42 . this circuit provides an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable by using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ( ) )/( 1 )(2/ r1r2 refin r r2r1drefin v n out ? ? ? ? ? ? ? ? ? + = where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. when refin = 5 v, r1 = r2 = 10 k, v out = (10 d /2 n ) ? 5 v +5v ad820/ op295 5v +5v r1 10k ? r2 10k ? sclk gnd serial interface ?5v +6v to +16v ad5307/ad5317/ ad5327 din 02067-042 sync v out a v out b v out c v out d v ref ab v ref cd 10f 0.1f gnd ref195 v in v out 1f v dd figure 42. bipolar operation with the ad5307/ad5317/ad5327
ad5307/ad5317/ad5327 rev. c | page 21 of 28 opto-isolated interface for process-control applications the ad5307/ad5317/ad5327 each have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process-control and industrial applications. due to noise, safety requirements, or distance, it may be necessary to isolate the ad5307/ad5317/ad5327 from the controller. this can easily be achieved by using opto-isolators capable of providing isolation in excess of 3 kv. the actual data rate achieved can be limited by the type of optocouplers chosen. the serial loading structure of the ad5307/ad5317/ad5327 makes them ideally suited for use in opto-isolated applications. figure 43 shows an opto-isolated interface to the ad5307/ad5317/ad5327 where din, sclk, and sync are driven from optocouplers. the power supply to the part should also be isolated. this is done by using a trans- former. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5307/ad5317/ ad5327. 10k ? din gnd sclk 5v regulator power 10k ? 10k ? ad5307 dcen 02067-043 sync v out b v out c v out d v ref ab v ref cd 10f 0.1f v out a v dd v dd v dd v dd sclk din syn c figure 43. ad5307 in an opto-isolated interface decoding multiple ad5307/ad5317/ad5327 devices the sync pin on the ad5307/ad5317/ad5327 can be used in applications to decode a number of dacs. in this application, all dacs in the system receive the same serial clock and serial data, but the sync to only one of the devices is active at any given time, allowing access to four channels in this 16-channel system. the 74hc139 is used as a 2-to-4 line decoder to address any of the dacs in the system. to prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 44 shows a diagram of a typical setup for decoding multiple ad5307 devices in a system. 74hc139 enable coded a ddress 1g 1a 1b dgnd 1y0 1y1 1y2 1y3 sclk din din sclk din sclk din sclk din sclk ad5307 ad5307 ad5307 ad5307 v out b v out c v out d v out a sync sync sync v cc v dd v out b v out c v out d v out a v out b v out c v out d v out a v out b v out c v out d v out a 02067-044 sync figure 44. decoding multiple ad5307 devices in a system ad5307/ad5317/ad5327 as digitally programmable window detectors a digitally programmable upper/lower limit detector using two of the dacs in the ad5307/ad5317/ad5327 is shown in figure 45 . the upper and lower limits for the test are loaded to dac a and dac b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led indicates the fail condition. similarly, dac c and dac d can be used for window detection on a second v in signal. 5v sclk din 1/2 cmp04 1k ? fail 1k ? pass 1/6 74hc05 sync 10f 0.1f v ref v in pass/fail ad5307/ ad5317/ ad5327 sclk din gnd v out a v ref ab v ref cd v out b sync v dd 02067-045 figure 45. window detection
ad5307/ad5317/ad5327 rev. c | page 22 of 28 daisy chaining for systems that contain several dacs, or where the user wishes to read back the dac contents for diagnostic purposes, the sdo pin can be used to daisy-chain several devices together and provide serial readback. figure 4 shows the timing diagram for daisy-chain applications. the daisy-chain mode is enabled by connecting dcen high (see figure 46 ). 1 additional pins omitted for clarity. 68hc11 1 miso din sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo din din ad5307 1 dcen dcen dcen sync sync sync ldac ldac ldac ad5307 1 ad5307 1 02067-046 figure 46. ad5307 in daisy-chain mode power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5307/ad5317/ad5327 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5307/ad5317/ad5327 are in a system where multiple devices require an agnd-to- dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5307/ad5317/ad5327 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), such as is typical of the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5307/ad5317/ad5327 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. com- ponents, such as clocks, with fast switching signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the refer- ence inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best, but it is not always possible with a double-sided board. in this technique, the com- ponent side of the board is dedicated to ground plane, and signal traces are placed on the solder side.
ad5307/ad5317/ad5327 rev. c | page 23 of 28 table 7. overview of ad53xx serial devices 1 part no. resolution no. of dacs dnl interface settling time (s) package pin singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 1 visit www.analog.com/support/standard_li near/selection_guides/ad53xx.html for more information. table 8. overview of ad53xx parallel devices additional pin functions part no. resolution dnl v ref pin settling time (s) buf gain hben clr package pin singles ad5330 8 0.25 1 6 ? ? ? tssop 20 ad5331 10 0.5 1 7 ? ? tssop 20 ad5340 12 1.0 1 8 ? ? ? tssop 24 ad5341 12 1.0 1 8 ? ? ? ? tssop 20 duals ad5332 8 0.25 2 6 ? tssop 20 ad5333 10 0.5 2 7 ? ? ? tssop 24 ad5342 12 1.0 2 8 ? ? ? tssop 28 ad5343 12 1.0 1 8 ? ? tssop 20 quads ad5334 8 0.25 2 6 ? ? tssop 24 ad5335 10 0.5 2 7 ? ? tssop 24 ad5336 10 0.5 4 7 ? ? tssop 28 ad5344 12 1.0 4 8 tssop 28
ad5307/ad5317/ad5327 rev. c | page 24 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 47. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
ad5307/ad5317/ad5327 rev. c | page 25 of 28 ordering guide model temperature range package description package option ad5307aru ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307aru-reel7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307aruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307aruz-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307bru ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307bru-reel ?40c to +105c 16-lead thin sh rink small outline package [tssop] ru-16 ad5307bru-reel7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307bruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307bruz-reel 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5307bruz-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317aru ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317aru-reel7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317aruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317bru ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317bru-reel ?40c to +105c 16-lead thin sh rink small outline package [tssop] ru-16 ad5317bru-reel7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317bruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317bruz-reel 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5317bruz-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327aru ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 AD5327ARU-REEL7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327aruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327bru ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327bru-reel ?40c to +105c 16-lead thin sh rink small outline package [tssop] ru-16 ad5327bru-reel7 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327bruz 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327bruz-reel 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 ad5327bruz-reel7 1 ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 1 z = pb-free part.
ad5307/ad5317/ad5327 rev. c | page 26 of 28 notes
ad5307/ad5317/ad5327 rev. c | page 27 of 28 notes
ad5307/ad5317/ad5327 rev. c | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02067C0C3/06(c)

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